Prior Art
Most communications between independent hardware components of a computer installation (from very simple units to sophisticated processing systems) takes place by a complex protocol insuring that the sending and receiving hardware components are synchronized. A channel is an example of such a communication means. This need for synchronization means that the receiving component must interrupt the work that it is performing, often at great cost to save and restore the status of the work.
A better alternative is to have some form of queuing mechanism for enabling the receiver to be decoupled from the sender. With a queue, a sender can transmit the data to the receiver's queue (enqueue) while the receiving hardware continues to do its normal function. At its own convenience, the receiving hardware can actually receive (dequeue) the transmitted data. Since the sending and receiving hardware components are independent entities capable of acting in parallel, and since the queue is, in effect, a shared resource, a lock normally is necessary to prevent the sender and receiver from interfering with each other during the enqueue and dequeue. This reduces the level of parallelism and the performance and also increases the complexity and the amount of information to be exchanged.
Generally, the lock between units, say A and B is implemented either:
explicitly, via Test And Set or Compare And Swap instructions if both A and B units are processors, (or any other kind of hardware or software implementation of semaphores), to allow either A or B to monopolize the queue during an enqueue or a dequeue manipulation, or PA1 implicitly, if both units use a single "Queue Manipulation Hardware" whose purpose is execute the enqueue and dequeue commands received from the units. Since this mechanism can execute only one command at a time, a serialism is performed. The lock is then implicitly implemented via this form of serialism.
U.S. Pat. No. 4,507,760 shows a FIFO memory configuration in which the lock is explicitly implemented. When both writing information into the FIFO queue and reading information from the FIFO queue are requested, a control circuit 26 gives priority to the write operation which eventually locks the communication between the queue and the receiving device.